The present invention generally relates to programmable circuit devices. More particularly, the present invention relates o a probe device for probing a circuit realized in silicon as a signal processor. While the invention is not to be limited thereto, the invention does particularly relate to the probing of a customized signal processing device having a novel architecture.
Digital signal processing has evolved from being an expensive, esoteric science used primarily in military applications such as radar systems, image recognition, and the like, to a high growth technology which is used in consumer products such as digital audio and the compact disk. Single chip digital signal processors (SCDSPs) were introduced in the early 1980's to specifically address these markets. However, SCDSPs are complex to use, and have significant performance limitations. In particular, while the requirements of signal processing are such that the signal processor be computationally intensive and controllable and have low latency and low parasitic overhead for real time I/O, and be able to efficiently execute multiple asynchronous processes, the signal processors of the art art burdened with the interrupt structures and the memory intensiveness of their microprocessor ancestors. The interrupt structures found in the SCDSPs of the art typically result in the SCDSPs being limited to a frequency spectrum from DC to the low tens of KHz.
In overcoming the problems of the SCDSPs of the art, a digital signal processor (also referred to as a "SPROC") architecture was set forth in parent application Ser. No. 07/525,977, where the interrupt structure is completely removed from the schedule of the computing processor(s)--e.g. the general signal processors or "GSPs". The separation is achieved by providing a central memory unit (data RAM) through which flows substantially all the data coming into and out of the signal processor, by providing a data flow manager (DFM) which handles I/O between the central memory unit and the "outside" world, and by providing an effectively multiported RAM so that access to the RAM by circuitry other than the computing processor(s) does not impact on the computing of the computing processor(s). The computing processor(s) is coupled to the central memory unit and does not communicate directly with the outside world; rather the computing processor(s) communicates via the central memory unit.
With the provided architecture of Ser. No. 07/525,977, and an appropriate compiler as set forth therein, a "sketch and realize" function can be obtained where the SPROC is automatically programmed to assume the function of a circuit sketched on a screen. Thus, the SPROC becomes a custom SCDSP, with the GSP(s) programmed to perform the desired functions.
In the development and debugging of an analog circuit, it is particularly useful to be able to determine the signal exiting any component of the circuit. In the development and debugging of an integrated circuit such as a digital signal processor where analog circuits are implemented by the digital signal processor as microcode which is executed by the digital signal processor, such probing is typically not available. To the extent that it is possible to arrange the microcode such that a signal at a "location" is provided to an output for viewing on an oscilloscope, there are numerous drawbacks. First, since the microcode used for providing the signal is typically undesired in the final product, the microcode uses up final product memory. An attempt to remove the signal producing microcode and replace it with other useful code for the final product is fruitless, as signals resulting from the other useful code cannot then be viewed, and in the process of removing the signal producing microcode, additional "bugs" may result. Second, based on the structure of present day digital signal processors, the task of probing numerous locations for viewing at an output is a time consuming one which requires numerous interrupts of the digital signal processor. As a result, the digital signal processor cannot function in its intended capacity. Thus, the digital signal processors of the art are not capable of providing a probe function while the digital signal processor is up and running.